Version:
~
[ SVN-2014-01-05 ] ~
[ 2.6.2 ] ~
** Warning: Cannot open xref database.
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios.h 11545 2012-11-11 08:11:17Z vruppert $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (C) 2006 Volker Ruppert
6 //
7 // This library is free software; you can redistribute it and/or
8 // modify it under the terms of the GNU Lesser General Public
9 // License as published by the Free Software Foundation; either
10 // version 2 of the License, or (at your option) any later version.
11 //
12 // This library is distributed in the hope that it will be useful,
13 // but WITHOUT ANY WARRANTY; without even the implied warranty of
14 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 // Lesser General Public License for more details.
16 //
17 // You should have received a copy of the GNU Lesser General Public
18 // License along with this library; if not, write to the Free Software
19 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
20
21 /* define it to include QEMU specific code */
22 //#define BX_QEMU
23
24 #ifndef LEGACY
25 # define BX_ROMBIOS32 1
26 #else
27 # define BX_ROMBIOS32 0
28 #endif
29
30 #define DEBUG_ROMBIOS 0
31 #define DEBUG_ATA 0
32 #define DEBUG_INT13_HD 0
33 #define DEBUG_INT13_CD 0
34 #define DEBUG_INT13_ET 0
35 #define DEBUG_INT13_FL 0
36 #define DEBUG_INT15 0
37 #define DEBUG_INT16 0
38 #define DEBUG_INT1A 0
39 #define DEBUG_INT74 0
40 #define DEBUG_APM 0
41
42 #define PANIC_PORT 0x400
43 #define PANIC_PORT2 0x401
44 #define INFO_PORT 0x402
45 #define DEBUG_PORT 0x403
46
47 #define BIOS_PRINTF_HALT 1
48 #define BIOS_PRINTF_SCREEN 2
49 #define BIOS_PRINTF_INFO 4
50 #define BIOS_PRINTF_DEBUG 8
51 #define BIOS_PRINTF_ALL (BIOS_PRINTF_SCREEN | BIOS_PRINTF_INFO)
52 #define BIOS_PRINTF_DEBHALT (BIOS_PRINTF_SCREEN | BIOS_PRINTF_INFO | BIOS_PRINTF_HALT)
53
54 #define printf(format, p...) bios_printf(BIOS_PRINTF_SCREEN, format, ##p)
55
56 // Defines the output macros.
57 // BX_DEBUG goes to INFO port until we can easily choose debug info on a
58 // per-device basis. Debug info are sent only in debug mode
59 #if DEBUG_ROMBIOS
60 # define BX_DEBUG(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p)
61 #else
62 # define BX_DEBUG(format, p...)
63 #endif
64 #define BX_INFO(format, p...) bios_printf(BIOS_PRINTF_INFO, format, ##p)
65 #define BX_PANIC(format, p...) bios_printf(BIOS_PRINTF_DEBHALT, format, ##p)
66
67 /* put the MP float table and ACPI RSDP in EBDA and the MP and ACPI tables in
68 high memory. Linux kernels < 2.6.30 might not work with this configuration */
69 //#define BX_USE_EBDA_TABLES
70
71 #define ACPI_DATA_SIZE 0x00010000L
72 #define MPTABLE_MAX_SIZE 0x00002000
73 #define PM_IO_BASE 0xb000
74 #define SMB_IO_BASE 0xb100
75 #define SMP_MSR_ADDR 0x0510
76
77 // Define the application NAME
78 #if defined(BX_QEMU)
79 # define BX_APPNAME "QEMU"
80 # define BX_APPVENDOR "QEMU"
81 #else
82 # define BX_APPNAME "Bochs"
83 # define BX_APPVENDOR "The Bochs Project"
84 #endif
85
86 #define E820_RAM 1
87 #define E820_RESERVED 2
88 #define E820_ACPI 3
89 #define E820_NVS 4
90 #define E820_UNUSABLE 5
91
92 #define BX_CPU 3
93 #define BX_USE_PS2_MOUSE 1
94 #define BX_CALL_INT15_4F 1
95 #define BX_USE_EBDA 1
96 #define BX_SUPPORT_FLOPPY 1
97 #define BX_FLOPPY_ON_CNT 37 /* 2 seconds */
98 #define BX_PCIBIOS 1
99 #define BX_APM 1
100 #define BX_PNPBIOS 1
101 /* define it if the (emulated) hardware supports SMM mode */
102 #define BX_USE_SMM
103
104 #define BX_USE_ATADRV 1
105 #define BX_ELTORITO_BOOT 1
106
107 #define BX_MAX_ATA_INTERFACES 4
108 #define BX_MAX_ATA_DEVICES (BX_MAX_ATA_INTERFACES*2)
109
110 #define BX_VIRTUAL_PORTS 1 /* normal output to Bochs ports */
111 #define BX_DEBUG_SERIAL 0 /* output to COM1 */
112
113 /* model byte 0xFC = AT */
114 #define SYS_MODEL_ID 0xFC
115 #define SYS_SUBMODEL_ID 0x00
116 #define BIOS_REVISION 1
117 #define BIOS_CONFIG_TABLE 0xe6f5
118
119 #ifndef BIOS_BUILD_DATE
120 # define BIOS_BUILD_DATE "06/23/99"
121 #endif
122
123 // 1K of base memory used for Extended Bios Data Area (EBDA)
124 // EBDA is used for PS/2 mouse support, and IDE BIOS, etc.
125 #define EBDA_SEG 0x9FC0
126 #define EBDA_SIZE 1 // In KiB
127 #define BASE_MEM_IN_K (640 - EBDA_SIZE)
128
129 /* IPL_SIZE bytes at 0x9ff00 are used for the IPL boot table. */
130 #define IPL_SEG 0x9ff0
131 #define IPL_TABLE_OFFSET 0x0000
132 #define IPL_TABLE_ENTRIES 8
133 #define IPL_COUNT_OFFSET 0x0080 /* u16: number of valid table entries */
134 #define IPL_SEQUENCE_OFFSET 0x0082 /* u16: next boot device */
135 #define IPL_BOOTFIRST_OFFSET 0x0084 /* u16: user selected device */
136 #define IPL_SIZE 0x86
137 #define IPL_TYPE_FLOPPY 0x01
138 #define IPL_TYPE_HARDDISK 0x02
139 #define IPL_TYPE_CDROM 0x03
140 #define IPL_TYPE_BEV 0x80
141
142 /* Ports */
143 #define PORT_DMA_ADDR_2 0x0004
144 #define PORT_DMA_CNT_2 0x0005
145 #define PORT_DMA1_MASK_REG 0x000a
146 #define PORT_DMA1_MODE_REG 0x000b
147 #define PORT_DMA1_CLEAR_FF_REG 0x000c
148 #define PORT_DMA1_MASTER_CLEAR 0x000d
149 #define PORT_PIC1_CMD 0x0020
150 #define PORT_PIC1_DATA 0x0021
151 #define PORT_PIT_COUNTER0 0x0040
152 #define PORT_PIT_MODE 0x0043
153 #define PORT_PS2_DATA 0x0060
154 #define PORT_PS2_CTRLB 0x0061
155 #define PORT_PS2_STATUS 0x0064
156 #define PORT_CMOS_INDEX 0x0070
157 #define PORT_CMOS_DATA 0x0071
158 #define PORT_DIAG 0x0080
159 #define PORT_DMA_PAGE_2 0x0081
160 #define PORT_A20 0x0092
161 #define PORT_PIC2_CMD 0x00a0
162 #define PORT_PIC2_DATA 0x00a1
163 #define PORT_DMA2_MASK_REG 0x00d4
164 #define PORT_DMA2_MODE_REG 0x00d6
165 #define PORT_DMA2_MASTER_CLEAR 0x00da
166 #define PORT_ATA2_CMD_BASE 0x0170
167 #define PORT_ATA1_CMD_BASE 0x01f0
168 #define PORT_FD_DOR 0x03f2
169 #define PORT_FD_STATUS 0x03f4
170 #define PORT_FD_DATA 0x03f5
171
172 #define CPUID_MSR (1 << 5)
173 #define CPUID_APIC (1 << 9)
174 #define CPUID_MTRR (1 << 12)
175
176 #define APIC_BASE ((uint8_t *)0xfee00000)
177 #define APIC_ICR_LOW 0x300
178 #define APIC_SVR 0x0F0
179 #define APIC_ID 0x020
180 #define APIC_LVT3 0x370
181
182 #define APIC_ENABLED 0x0100
183
184 #define AP_BOOT_ADDR 0x9f000
185
186 #define SMI_CMD_IO_ADDR 0xb2
187
188 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
189
190 #define MSR_MTRRcap 0x000000fe
191 #define MSR_MTRRfix64K_00000 0x00000250
192 #define MSR_MTRRfix16K_80000 0x00000258
193 #define MSR_MTRRfix16K_A0000 0x00000259
194 #define MSR_MTRRfix4K_C0000 0x00000268
195 #define MSR_MTRRfix4K_C8000 0x00000269
196 #define MSR_MTRRfix4K_D0000 0x0000026a
197 #define MSR_MTRRfix4K_D8000 0x0000026b
198 #define MSR_MTRRfix4K_E0000 0x0000026c
199 #define MSR_MTRRfix4K_E8000 0x0000026d
200 #define MSR_MTRRfix4K_F0000 0x0000026e
201 #define MSR_MTRRfix4K_F8000 0x0000026f
202 #define MSR_MTRRdefType 0x000002ff
203
204 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
205 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
206
207 #define MTRR_MEMTYPE_UC 0
208 #define MTRR_MEMTYPE_WC 1
209 #define MTRR_MEMTYPE_WT 4
210 #define MTRR_MEMTYPE_WP 5
211 #define MTRR_MEMTYPE_WB 6
212
213 #define QEMU_CFG_CTL_PORT 0x510
214 #define QEMU_CFG_DATA_PORT 0x511
215 #define QEMU_CFG_SIGNATURE 0x00
216 #define QEMU_CFG_ID 0x01
217 #define QEMU_CFG_UUID 0x02
218
219 #define PCI_ADDRESS_SPACE_MEM 0x00
220 #define PCI_ADDRESS_SPACE_IO 0x01
221 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
222
223 #define PCI_ROM_SLOT 6
224 #define PCI_NUM_REGIONS 7
225
226 #define PCI_DEVICES_MAX 64
227
228 #define PCI_CLASS_STORAGE_IDE 0x0101
229 #define PCI_CLASS_DISPLAY_VGA 0x0300
230 #define PCI_CLASS_SYSTEM_PIC 0x0800
231
232 #define PCI_VENDOR_ID 0x00 /* 16 bits */
233 #define PCI_DEVICE_ID 0x02 /* 16 bits */
234 #define PCI_COMMAND 0x04 /* 16 bits */
235 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
236 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
237 #define PCI_CLASS_DEVICE 0x0a /* Device class */
238 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
239 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
240 #define PCI_MIN_GNT 0x3e /* 8 bits */
241 #define PCI_MAX_LAT 0x3f /* 8 bits */
242
243 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
244
245 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
246 #define PCI_ROM_ADDRESS_ENABLE 0x01
247
248 #define PCI_VENDOR_ID_INTEL 0x8086
249 #define PCI_DEVICE_ID_INTEL_82437 0x0122
250 #define PCI_DEVICE_ID_INTEL_82441 0x1237
251 #define PCI_DEVICE_ID_INTEL_82371FB_0 0x122e
252 #define PCI_DEVICE_ID_INTEL_82371FB_1 0x1230
253 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
254 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
255 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
256 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
257 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
258
259 #define PCI_VENDOR_ID_IBM 0x1014
260 #define PCI_VENDOR_ID_APPLE 0x106b
261
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